In semiconductor technologies, a plurality of photomasks (masks) is formed with predesigned integrated circuit (IC) patterns. The plurality of masks is used to transfer those predesigned IC patterns to semiconductor wafers in lithography processes. The predesigned IC patterns formed on masks are master patterns. Any defect on a mask will be transferred to multiple semiconductor wafers and cause yield issues and quality concerns.
The mask defects include mask haze introduced during lithography processes. A wafer patterned with a defected mask may be scraped, increasing the manufacturing cost. To avoid wafer scrape from the mask haze, periodic mask haze inspection is used to periodically check a mask, such as after every few hundreds exposed wafers. This introduces a mask inspection cost and increases the wafer cycle time.
Other issues associated with mask include mask defocus on mask chuck. To avoid wafer scrape from the mask defocus, periodic mask shape measurement is used to check a mask, which introduces a mask shape measurement cost and further increases the wafer cycle time.
Therefore, a system and a method for lithography pattering are needed to address the above issues.